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DS021 (v2.2) June 25, 2000
Product Specification
Product Features
* * Certified to MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing) Also available under the following Standard Microcircuit Drawings (SMD) XC4005E 5962-97522 XC4010E 5962-97523 XC4013E 5962-97524 XC4025E 5962-97525 XC4028EX 5962-98509 For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with * Synchronous write option * Dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks System Performance beyond 60 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA sink current per XQ4000E/EX output * * Configured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verification - Internal node observability Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Available Speed Grades: - XQ4000E -3 for plastic packages only -4 for ceramic packages only - XQ4028EX -4 for all packages
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More Information
For more information refer to Xilinx XC4000E and XC4000X series Field Programmable Gate Arrays product specification. This data sheet contains pinout tables for XQ4010E only. Refer to Xilinx web site for pinout tables for other devices. (Pinouts for XQ4000E/EX are identical to XC4000E/EX.) (http://www.xilinx.com/partinfo/databook.htm)
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(c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS021 (v2.2) June 25, 2000 Product Specification
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Table 1: XQ4000E/EX Field Programmable Gate Arrays Max. Max. Logic RAM Bits Gates (No (No RAM) Logic) 5,000 10,000 6,272 12,800 Typical Gate Range (Logic and RAM)(1) 3,000 - 9,000 7,000 - 20,000 Number of Flip-Flops 616 1,120 Max. Decode Inputs per Side 42 60 Max. User I/O 112 160
Device XQ4005E XQ4010E
CLB Matrix 14 x 14 20 x 20
Total CLBs 196 400
Packages PG156, CB164 PG191, CB196, HQ208 PG223, CB228, HQ240 PG299, CB228 PG299, CB228, HQ240, BG352
XQ4013E
13,000
18,432
10,000 - 30,000 24 x 24
576
1,536
72
192
XQ4025E XQ4028EX
25,000 28,000
32,768 32,768
15,000 - 45,000 32 x 32 18,000 - 50,000 32 x 32
1,024 1,024
2,560 2,560
96 96
256 256
Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings(1)
Symbol VCC VIN VTS TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND(2) Voltage applied to High-Z output(2) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic package Plastic package Description -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 +150 +125 Units V V V C C C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC excursion above V CC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to VCC + 2.0V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E Recommended Operating Conditions(1,2)
Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = -55C to +125C Supply voltage relative to GND, TC = -55C to +125C High-Level Input Voltage Plastic Ceramic TTL inputs CMOS inputs Low-Level Input Voltage TTL inputs CMOS inputs Input signal transition time Min 4.5 4.5 2.0 70% 0 0 Max 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol VOH VOL ICCO IL CIN IRIN IRLL Description High-level output voltage @ IOH = -4.0 mA, VCC min High-level output voltage @ IOH = -1.0 mA, VCC min Low-level output voltage @ IOL = 12.0 mA, VCC min(1) Quiescent FPGA supply current(2) TTL outputs CMOS outputs TTL outputs CMOS outputs Min 2.4 VCC - 0.5 -10 -0.02 0.2 Low(3) Max 0.4 0.4 50 +10 16 -0.25 2.5 Units V V V V mA A pF mA mA
Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) at VIN = 0V (sample tested)(3) Horizontal longline pull-up (when selected) at logic
Notes: 1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins. 2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA configured with the development system Tie option. 3. Characterized Only.
DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Note: -3 Speed Grade only applies to XQ4010E and XQ4013E Plastic Package options only. -4 Speed Grade applies to all XQ devices and is only available in Ceramic Packages only.
XQ4000E Global Buffer Switching Characteristics
-3(1) Symbol TPG Description From pad through primary buffer, to any clock K Device XQ4005E XQ4010E XQ4013E XQ4025E TSG From pad through secondary buffer, to any clock K XQ4005E XQ4010E XQ4013E XQ4025E
Notes: 1. For plastic package options only. 2. For ceramic package options only.
-4(2) Max 7.0 11.0 11.5 12.5 7.5 11.5 12.0 13.0 Units ns ns ns ns ns ns ns ns
Max 6.3 6.8 6.8 7.3 -
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. -3 Symbol TIO1 Description I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active.(1) Device XQ4005E XQ4010E XQ4013E XQ4025E TIO2 I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain.(1) XQ4005E XQ4010E XQ4013E XQ4025E TON T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low.(1) XQ4005E XQ4010E XQ4013E XQ4025E TOFF T going High to TBUF going inactive, not driving LL. XQ4005E XQ4010E XQ4013E XQ4025E TPUS T going High to LL going from Low to High, pulled up by a single resistor.(1) XQ4005E XQ4010E XQ4013E XQ4025E TPUF T going High to LL going from Low to High, pulled up by two resistors.(1) XQ4005E XQ4010E XQ4013E XQ4025E Max 6.4 7.2 6.9 7.7 7.3 7.5 1.5 1.5 22.0 26.0 11.0 13.0 -4 Max 5.0 8.0 9.0 11.0 6.0 10.5 11.0 12.0 7.0 8.5 8.7 11.0 1.8 1.8 1.8 1.8 23.0 29.0 32.0 42.0 10.0 13.5 15.0 18.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TBUF Driving a Horizontal Longline (LL):
Notes: 1. These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. -3 Symbol TWAF Description(1,2) Full length, both pull-ups, inputs from IOB I-pins Device XQ4005E XQ4010E XQ4013E XQ4025E TWAFL Full length, both pull-ups, inputs from internal logic XQ4005E XQ4010E XQ4013E XQ4025E TWAO Half length, one pull-up, inputs from IOB I-pins XQ4005E XQ4010E XQ4013E XQ4025E TWAOL Half length, one pull-up, inputs from internal logic XQ4005E XQ4010E XQ4013E XQ4025E Max 9.0 11.0 11.0 13.0 10.0 12.0 12.0 14.0 -4 Max 9.5 15.0 16.0 18.0 12.5 18.0 19.0 21.0 10.5 16.0 17.0 19.0 12.5 18.0 19.0 21.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These delays are specified from the decoder input to the decoder output. 2. Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
-3 Symbol
Combinatorial Delays
-4 Max 2.01 4.3 3.3 3.6 3.6 2.6 4.4 1.7 3.3 0.7 2.8 Min 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 2.5 4.2 Max 2.7 4.7 4.1 3.7 4.5 3.2 5.5 1.7 3.8 1.0 3.7 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via SR through H to X/Y outputs C inputs via H to X/Y outputs C inputs via DIN through H to X/Y outputs Operand inputs (F1, F2, G1, G4) to C OUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Clock K to outputs Q F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H
Min 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 2.1 3.5
TILO TIHO THH0O THH1O THH2O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK
CLB Fast Carry Logic
Sequential Delays
Setup Time before Clock K
DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E CLB Switching Characteristic Guidelines (continued)
-3 Symbol
Hold Time after Clock K
-4 Max 4.0 18.7 18.7 125 Min 0 0 0 0 0 0 0 0 4.5 4.5 5.5 13.0 Max 6.5 23.0 23.0 111 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Description F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock High time Clock Low time Width (High) Delay from C inputs via S/R, going High to Q Width (High or Low) Delay from Global Set/Reset net to Q Global Set/Reset inactive to first active clock K edge Toggle Frequency(2)
Min 0 0 0 0 0 0 0 0 4.0 4.0 4.0 11.5 -
TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR
Clock
TCH TCL TRPW TRIO Master TMRW TMRQ TMRK FTOG
Set/Reset Direct
Set/Reset(1)
Notes: 1. Timing is based on the XC4005E. For other devices see the static timing analyzer. 2. Export Control Max. flip-flop toggle rate.
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 Symbol TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS Data valid after clock K WE hold time after clock K WE setup time before clock K DIN hold time after clock K DIN setup time before clock K Address hold time after clock K Address setup time before clock K Clock K pulse width (active edge) Write Operation Description Address write cycle time (clock K period) Size 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 Min 14.4 14.4 7.2 7.2 2.4 2.4 0 0 3.2 1.9 0 0 2.0 2.0 0 0 8.8 10.3 Max 1 ms 1 ms Min 15.0 15.0 7.5 7.5 2.8 2.8 0 0 3.5 2.5 0 0 2.2 2.2 0 0 -4 Max 1 ms 1 ms 10.3 11.6 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3 Symbol TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS Write Operation Description Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Size(1) 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 Min 14.4 7.2 2.5 0 2.5 0 1.8 0 1 ms 7.8 Max Min 15.0 7.5 2.8 0 2.2 0 2.2 0.3 1 ms 10.0 -4 Max Units ns ns ns ns ns ns ns ns ns
Notes: 1. Applicable Read timing specifications are identical to Level-Sensitive Read timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 9
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XQ4000E CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TAHS TDHS TWHS
TILO DATA OUT
TILO TWOS
OLD NEW
DS021_01_060100
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
TWPDS WCLK (K) TWSS WE TDSDS DATA IN TASDS ADDRESS TAHDS TDHDS TWHS
TILO DATA OUT
TILO TWODS
OLD NEW
DS021_02_060100
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000E devices unless otherwise noted.
-3 Symbol
Write Operation
-4 Max 1.8 3.2 6.0 7.3 6.6 7.6 Min 8.0 8.0 4.0 4.0 2.0 2.0 2.5 2.0 4.0 5.0 2.0 2.0 4.5 6.5 4.0 6.1 8.0 9.6 7.0 8.0 Max 2.7 4.7 10.0 12.0 9.0 11.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Single Port RAM Address write cycle time
Size 16x2 32x1
Min 8.0 8.0 4.0 4.0 2.0 2.0 2.0 2.0 2.2 2.2 2.0 2.0 3.1 5.5 3.0 4.6 6.0 6.8 5.2 6.2
TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT
Write Enable pulse width (High)
16x2 32x1
Address setup time before WE
16x2 32x1
Address hold time after end of WE
16x2 32x1
DIN setup time before end of WE DIN hold time after end of WE
16x2 32x1 16x2 32x1
Read Operation
TRC TRCT TILO TIHO
Address read cycle time
16x2 32x1
Data valid after address change (no Write Enable)
16x2 32x1
Read Operation, Clocking Data into Flip-Flop
TICK TIHCK
Address setup time before clock K
16x2 32x1
Read During Write
TWO TWOT TDO TDOT
Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE)
16x2 32x1 16x2 32x1
Read During Write, Clocking Data into Flip-Flop
TWCK TWCKT TDCK TDOCK
WE setup time before clock K
16x2 32x1
Data setup time before clock K
16x2 32x1
Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 11
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XQ4000E CLB Level-Sensitive RAM Timing Characteristics
WRITE ADDRESS TAS WE TDS DATA IN READ WITHOUT WRITE TILO X,Y OUTPUTS
VALID VALID REQUIRED
TWC
TWP
TAH
TDH
READ, CLOCKING DATA INTO FLIP-FLOP TICK CLOCK TCKO XQ,YQ OUTPUTS READ DURING WRITE WRITE ENABLE TDH DATA IN (stable during WE) TWO X,Y OUTPUTS DATA IN (changing during WE) X,Y OUTPUTS
VALID VALID VALID (OLD) VALID (NEW)
TCH
TWP
OLD
NEW
TWO
VALID (PREVIOUS) VALID (OLD)
TDO
VALID (NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP TWP WRITE ENABLE TWCK TDCK DATA IN
CLOCK TCKO XQ,YQ OUTPUTS
DS021_03_060100
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DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and Symbol TICKOF (Max)
TPG OFF
worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000E devices unless otherwise noted. Device XQ4005E XQ4010E XQ4013E XQ4025E -3 10.9 11.0 -4 14.0 16.0 16.5 17.0 Units ns ns ns ns
Description Global clock to output (fast) using OFF
Global Clock-to-Output Delay
DS021_04_060100
TICKO (Max)
Global clock to output (slew-limited) using OFF
TPG OFF
XQ4005E XQ4010E XQ4013E XQ4025E
14.9 15.0 -
18.0 20.0 20.5 21.0
ns ns ns ns
Global Clock-to-Output Delay
DS021_04_060100
TPSUF (Min)
Input setup time, using IFF (no delay)
Input Setup and Hold Time D
TPG
IFF
XQ4005E XQ4010E XQ4013E XQ4025E
0.2 0 -
2.0 1.0 0.5 0
ns ns ns ns
DS021_05_060100
TPHF (Min)
Input hold time, using IFF (no delay)
Input Setup and Hold Time D
TPG
IFF
XQ4005E XQ4010E XQ4013E XQ4025E
5.5 6.5 -
4.6 6.0 7.0 8.0
ns ns ns ns
DS021_05_060100
TPSU (Min)
Input setup time, using IFF (with delay)
Input Setup and Hold Time D
TPG
IFF
XQ4005E XQ4010E XQ4013E XQ4025E
7.0 7.0 -
8.5 8.5 8.5 9.5
ns ns ns ns
DS021_05_060100
TPH (Min)
Input hold time, using IFF (with delay)
Input Setup and Hold Time D
TPG
IFF
XQ4005E XQ4010E XQ4013E XQ4025E
0 0 -
0 0 0 0
ns ns ns ns
DS021_05_060100
Notes: 1. OFF = Output Flip-Flop 2. IFF = Input Flip-Flop or Latch
DS021 (v2.2) June 25, 2000 Product Specification
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XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000E devices unless otherwise noted.
-3 Symbol TPID TPLI TPDLI Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, with delay Description Device All devices All devices XQ4005E XQ4010E XQ4013E XQ4025E
Propagation Delays (CMOS Inputs)(1)
-4 Max 2.5 3.6 10.8 11.2 4.1 8.8 14.0 14.4 2.8 4.0 Min 0 0 1.5 0 Max 3.0 4.8 10.8 11.0 11.4 13.8 5.5 6.8 16.5 17.5 18.0 20.8 5.6 6.2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min 0 0 1.5 0
Propagation Delays (TTL Inputs)(1)
TPIDC TPLIC TPDLIC
Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, with delay
All devices All devices XQ4005E XQ4010E XQ4013E XQ4025E
Propagation Delays (TTL Inputs)
TIKRI TIKLI TIKPI TIKPID TIKEC TIKECD
Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Pad to clock (IK), no delay Pad to clock (IK), with delay Clock enable (EC) to clock (K), no delay Clock enable (EC) to clock (K), with delay
All devices All devices All devices All devices All devices All devices
Hold Times(2)
Notes: 1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Input Switching Characteristic Guidelines (continued)
-3 Symbol
Setup Times (TTL Inputs)(1,2)
-4 Max 7.8 Min 4.0 10.9 11.3 11.8 14.0 6.0 12.0 13.0 13.5 16.0 3.5 10.4 10.7 11.1 14.0 13.0 13.0 Max 12.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Pad to clock (IK), no delay Pad to clock (IK), with delay
Device All devices XQ4005E XQ4010E XQ4013E XQ4025E
Min 2.6 9.8 10.2 3.3 10.5 10.9 2.5 9.7 10.1 11.5 11.5
TPICK TPICKD
Setup Times (CMOS
Inputs)(1,2)
TPICKC TPICKDC
Pad to clock (IK), no delay Pad to clock (IK), with delay
All devices XQ4005E XQ4010E XQ4013E XQ4025E
(TTL or CMOS)
TECIK TECIKD
Clock enable (EC) to clock (IK), no delay Clock enable (EC) to clock (IK), with delay
All devices XQ4005E XQ4010E XQ4013E XQ4025E
Global
Set/Reset(3)
TRRI TMRW TMRI
Delay from GSR net through Q to I1, I2 GSR width GSR inactive to first active clock (IK) edge
All devices All devices All devices
Notes: 1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
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XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XQ4000E devices unless otherwise noted. -3 Symbol TOKPOF TOKPOS TOPF TOPS TTSHZ TTSONF TTSONS TOKPOFC TOKPOSC TOPFC TOPSC TTSHZC TTSONFC TTSONSC TOOK TOKO TECOK TOKEC
Clock
-4 Max 6.5 9.5 5.5 8.6 4.2 8.1 11.1 7.8 11.6 9.7 13.4 4.3 7.6 11.4 11.8 Min 5.0 0 4.8 1.2 4.5 4.5 13.0 13.0 Max 7.5 11.5 8.0 12.0 10.0 10.0 13.7 9.5 13.5 10.0 14.0 5.2 9.1 13.1 15.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Clock (OK) to pad, fast Clock (OK) to pad, slew-rate limited Output (O) to pad, fast Output (O) to pad, slew-rate limited 3-state to pad High-Z, slew-rate independent 3-state to pad active and valid, fast 3-state to pad active and valid, slew-rate limited Clock (OK) to pad, fast Clock (OK) to pad, slew-rate limited Output (O) to pad, fast Output (O) to pad, slew-rate limited 3-state to pad High-Z, slew-rate independent 3-state to pad active and valid, fast 3-state to pad active and valid, slew-rate limited Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock enable (EC) to clock (OK) setup Clock enable (EC) to clock (OK) hold Clock High Clock Low
Min 4.6 0 3.5 1.2 4.0 4.0 11.5 11.5
Propagation Delays (TTL Output Levels)
Propagation Delays (CMOS Output Levels)
Setup and Hold Times
TCH TCL
Global
Set/Reset(3)
TRRO TMRW TMRO
Delay from GSR net to pad GSR width GSR inactive to first active clock (OK) edge
Notes: 1. Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm. 2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
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DS021 (v2.2) June 25, 2000 Product Specification
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF-S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted.
-3 Symbol
Setup Times
-4 Max Min 30.0 15.0 0 0 30.0 30.0 5.0 5.0 15.0 15.0 Max Units ns ns ns ns ns ns ns MHz
Description Input (TDI) to clock (TCK) Input (TMS) to clock (TCK) Input (TDI) to clock (TCK) Input (TMS) to clock (TCK) Clock (TCK) to pad (TDO) Clock (TCK) High Clock (TCK) Low Frequency
Min 30.0 15.0 0 0
TTDITCK TTMSTCK
Hold Times
TTCKTDI TTCKTMS
Propagation Delay
TTCKPO
Clock
TTCKH TTCKL FMAX
5.0 5.0
Notes: 1. Input setup and hold times and clock-to-pad times are specified with respect to external signal pins. 2. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. 3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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XQ4028EX Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the A.C. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice.
XQ4028EX Absolute Maximum Ratings(1)
Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND(2) Voltage applied to High-Z output(2) Longest supply voltage rise time from 1V to 4V Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic package Plastic package Description -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 50 -65 to +150 +260 +150 +125 Units V V V ms C C C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC excursion above V CC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. Maximum total combined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the device pins may undershoot to -2.0V or overshoot toV CC +2.0V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Recommended Operating Conditions(1)
Symbol VCC VIH VIL TIN Descriptiont Supply voltage relative to GND, TJ = -55C to +125C Supply voltage relative to GND, TC = -55C to +125C High-level input voltage(2) Plastic Ceramic TTL inputs CMOS inputs Low-level input voltage TTL inputs CMOS inputs Input signal transition time Min 4.5 4.5 2.0 70% 0 0 Max 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
XQ4028EX DC Characteristics Over Recommended Operating Conditions
Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL Description High-level output voltage at IOH = -4 mA, VCC min High-level output voltage at IOH = -1 mA Low-level output voltage at IOL = 12 mA, VCC min(1) TTL outputs CMOS outputs TTL outputs CMOS outputs Data retention supply voltage (below which configuration data may be lost) Quiescent FPGA supply current(2) Min 2.4 VCC - 0.5 3.0 -10 Plastic packages Ceramic packages Pad pull-up (when selected) at VIN = 0V (sample tested) Pad pull-down (when selected) at VIN = 5.5V (sample tested) Horizontal longline pull-up (when selected) at logic Low(3) 0.02 0.02 0.3 Max 0.4 0.4 25 10 10 16 0.25 0.25 2.0 Units V V V V V mA A V V mA mA mA
Input or output leakage current Input capacitance (sample tested)
Notes: 1. With up to 64 pins simultaneously sinking 12 mA. 2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND.
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XQ4028EX Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature)
Global Buffer Switching Characteristics.
-4 Symbol TGLS TGE Description From pad through Global Low Skew buffer, to any clock K From pad through Global Early buffer, to any clock K in same quadrant Max 9.2 5.7 Units ns ns
XQ4028EX Horizontal Longline Switching Characteristic Guidelines
-4 Symbol
TBUF Driving a Horizontal Longline
Description I going High or Low to horizontal longline going High or Low, while T is Low. Buffer is constantly active. T going Low to horizontal longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer is constantly active. T going Low to half of a horizontal longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low.
Max 13.7 14.7
Units ns ns
TIO1 TON
TBUF Driving Half a Horizontal Longline
THIO1 THON
6.3 7.2
ns ns
Notes: 1. These values include a minimum load of one output, spaced as far as possible from the activated pull-up(s). Use the static timing analyzer to determine the delay for each destination.
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted.
CLB Switching Characteristics
-4 Symbol
Combinatorial Delays
Description F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) Operand inputs (F1, F2, G1, G4) to C OUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry net selay, COUT to CIN Clock K to flip-flop outputs Q Clock K to latch outputs Q F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H F/G inputs
Min 1.3 3.0 2.8 2.2 2.8 1.2 1.2 0.8 2.2 3.9 0
Max 2.2 3.8 3.2 3.6 3.0 3.6 2.0 2.5 4.1 1.9 3.0 0.60 0.18 2.2 2.2 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI
CLB Fast Carry Logic
Sequential Delays
Setup Time before Clock K
Hold Time after Clock K
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CLB Switching Characteristics (Continued)
-4 Symbol TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR
Clock
Description F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock High time Clock Low time Width (High) Delay from C inputs via S/R, going High to Q Minimum GSR pulse width Delay from GSR input to any Q Toggle frequency (MHz) (for export control)
Min 0 0 0 0 0 0 0 3.5 3.5 3.5 -
Max 4.5 13.0 22.8 143
Units ns ns ns ns ns ns ns ns ns ns ns ns
TCH TCL
Set/Reset Direct
TRPW TRIO TMRW TMRQ FTOG
Global Set/Reset
MHz
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted.
-4 Symbol
Write Operation
Single Port RAM Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Size 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1
Min 11.0 11.0 5.5 5.5 2.7 2.6 0 0 2.4 2.9 0 0 2.3 2.1 0 0 -
Max 8.2 10.1
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS
Notes: 1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-4 Symbol
Write Operation
Dual Port RAM Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K
Size(1) 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1
Min 11.0 5.5 3.1 0 2.9 0 2.1 0 -
Max
Units ns
TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS
9.4
ns ns ns ns ns ns ns ns
Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
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XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TAHS TDHS TWHS
TILO DATA OUT
TILO TWOS
OLD NEW
DS021_01_060100
XQ4028EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
TWPDS WCLK (K) TWSS WE TDSDS DATA IN TASDS ADDRESS TAHDS TDHDS TWHS
TILO DATA OUT
TILO TWODS
OLD NEW
DS021_02_060100
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DS021 (v2.2) June 25, 2000 Product Specification
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted.
-4 Symbol
Write Operation
Single Port RAM Address write cycle time
Size 16x2 32x1
Min 10.6 10.6 5.3 5.3 2.8 2.8 1.7 1.7 1.1 1.1 6.6 6.6 4.5 6.5 1.5 3.2 7.1 9.2 5.9 8.4
Max 2.2 3.8 6.5 7.4 7.7 8.2 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT
Write Enable pulse width (High)
16x2 32x1
Address setup time before WE
16x2 32x1
Address hold time after end of WE
16x2 32x1
DIN setup time before end of WE
16x2 32x1
DIN hold time after end of WE
16x2 32x1
Read Operation
TRC TRCT TILO TIHO
Address read cycle time
16x2 32x1
Data valid after address change (no Write Enable)
16x2 32x1
Read Operation, Clocking Data into Flip-Flop
TICK TIHCK
Address setup time before clock K
16x2 32x1
Read During Write
TWO TWOT TDO TDOT
Data valid after WE goes active (DIN stable before WE)
16x2 32x1
Data valid after DIN (DIN changes during WE)
16x2 32x1
Read During Write, Clocking Data into Flip-Flop
TWCK TWCKT TDCK TDOCK
WE setup time before clock K
16x2 32x1
Data setup time before clock K
16x2 32x1
Notes: 1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing. DS021 (v2.2) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 25
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XQ4028EX CLB Level-Sensitive RAM Timing Waveforms
WRITE ADDRESS TAS WE TDS DATA IN READ WITHOUT WRITE TILO X,Y OUTPUTS
VALID VALID REQUIRED
TWC
TWP
TAH
TDH
READ, CLOCKING DATA INTO FLIP-FLOP TICK CLOCK TCKO XQ,YQ OUTPUTS READ DURING WRITE WRITE ENABLE TDH DATA IN (stable during WE) TWO X,Y OUTPUTS DATA IN (changing during WE) X,Y OUTPUTS
VALID VALID VALID (OLD) VALID (NEW)
TCH
TWP
OLD
NEW
TWO
VALID (PREVIOUS) VALID (OLD)
TDO
VALID (NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP TWP WRITE ENABLE TWCK TDCK DATA IN
CLOCK TCKO XQ,YQ OUTPUTS
DS021_03_060100
Figure 1:
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DS021 (v2.2) June 25, 2000 Product Specification
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000EX devices unless otherwise noted.
XQ4028EX Output Flip-Flop, Clock to Out(1,2)
-4 Symbol TICKOF TICKEOF Description Global low skew clock to output using OFF(3) Global early clock to output using OFF(3) Max 16.6 13.1 Units ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at TTL threshold with 50 pF external capacitive load. 3. OFF = Output Flip-Flop
XQ4028EX Output Mux, Clock to Out(1,2)
-4 Symbol TPFPF TPEFPF Description Global low skew clock to TTL output (fast) using OMUX3) Global early clock to TTL output (fast) using OMUXF(3) Max 15.9 12.4 Units ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. For different loads, see graph below. 3. OMUX = Output MUX
XQ4028EX Output Level and Slew Rate Adjustments
The following table must be used to adjust output parameters and output switching characteristics. -4 Symbol TTTLOF TTTLO TCMOSOF TCMOSO For TTL output FAST add For TTL output SLOW add For CMOS FAST output add For CMOS SLOW output add Description Max 0 2.9 1.0 3.6 Units ns ns ns ns
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XQ4028EX Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XQ4000EX devices unless otherwise noted
XQ4028EX Global Low Skew Clock, Setup and Hold
-4 Symbol TPSD TPHD Description Input setup time, using Global Low Skew clock and IFF (full delay) Input hold time, using Global Low Skew clock and IFF (full delay) Min 8.0 0 Units ns ns
Notes: 1. IFF = Flip-Flop or Latch
XQ4028EX Global Early Clock, Setup and Hold for IFF
-4 Symbol TPSEP TPHEP Description Input setup time, using Global Early clock and IFF (full delay) Input hold time, using Global Early clock and IFF (full delay) Min(2) 6.5 0 Units ns ns
Notes: 1. IFF = Flip-Flop or Latch 2. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.
XQ4028EX Global Early Clock, Setup and Hold for FCL
-4 Symbol TPFSEP TPFHEP Description Input setup time, using Global Early clock and FCL (partial delay) Input hold time, using Global Early clock and FCL (partial delay) Min(2) 3.4 0 Units ns ns
Notes: 1. FCL = Fast Capture Latch 2. For CMOS input levels, see the XQ4028EX Input Threshold Adjustments. 3. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time under given design conditions. 4. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. 5. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.
XQ4028EX Input Threshold Adjustments
The following table must be used to adjust input parameters and input switching characteristics. -4 Symbol TTTLI TCMOSI For TTL input add For CMOS input add Description Max 0 0.3 Units ns ns
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XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000EX devices unless otherwise noted.
-4 Symbol
Clocks
Description Delay from FCL enable (OK) active to IFF clock (IK) active edge Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent input latch, partial delay Pad to I1, I2 via transparent input latch, full delay Pad to I1, I2 via transparent FCL and input latch, no delay Pad to I1, I2 via transparent FCL and input latch, partial delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL enable (OK) active edge to I1, I2 (via transparent standard input latch) Minimum GSR pulse width Delay from GSR input to any Q
Min 3.2 2.2 3.8 13.3 18.2 5.3 13.6 3.0 3.2 6.2 13.0 22.8
Units ns ns ns ns ns ns ns ns ns ns ns ns
TOKIK TPID TPLI TPPLI TPDLI TPFLI TPPFLI TIKRI TIKLI TOKLI TMRW TRRI
Propagation Delays
Propagation Delays (TTL Inputs)
Global Set/Reset
Notes: 1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch 2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28. 3. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold tables on page 28.
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XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
-4 Symbol
Setup Times
Description Pad to Clock (IK), no delay Pad to Clock (IK), partial delay Pad to Clock (IK), full delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Clock (IK), via transparent Fast Capture Latch, partial delay Pad to Fast Capture Latch Enable (OK), no delay Pad to Fast Capture Latch Enable (OK), partial delay Clock Enable (EC) to Clock (IK) Pad to Clock (IK), no delay Pad to Clock (IK), partial delay Pad to Clock (IK), full delay Pad to Clock (IK) via transparent Fast Capture Latch, no delay Pad to Clock (IK) via transparent Fast Capture Latch, partial delay Pad to Clock (IK) via transparent Fast Capture Latch, full delay Clock Enable (EC) to Clock (IK), no delay Clock Enable (EC) to Clock (IK), partial delay Clock Enable (EC) to Clock (IK), full delay Pad to Fast Capture Latch Enable (OK), no delay Pad to Fast Capture Latch Enable (OK), partial delay
Min 2.5 10.8 15.7 3.9 12.3 0.8 9.1 0.3 0 0 0 0 0 0 0 0 0 0 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TPICK TPICKP TPICKD TPICKF TPICKFP TPOCK TPOCKP TECIK
Hold Times
Setup Times (TTL or CMOS Inputs)
TIKPI TIKPIP TIKPID TIKPIF TIKFPIP TIKFPID TIKEC TIKECP TIKECD TOKPI TOKPIP
Notes: 1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28. 2. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold tables on page 28.
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FXQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XQ4000EX devices unless otherwise noted. -4 Symbol
Propagation Delays (TTL Output Levels)
Description Clock (OK) to pad, fast Output (O) to pad, fast 3-state to pad High-Z, slew-rate independent 3-state to pad active and valid, fast Output MUX select (OK) to pad Fast path output MUX input (EC) to pad Slowest path output MUX input (EC) to pad Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock enable (EC) to clock (OK) setup Clock enable (EC) to clock (OK) hold Clock High Clock Low Minimum GSR pulse width Delay from GSR input to any pad
Min 0.6 0 0 0 3.5 3.5 13.0 30.2
Max 7.4 6.2 4.9 6.2 6.7 6.2 7.3 -
Units ns ns ns ns ns
TOKPOF TOPF TTSHZ TTSONF TOKFPF TCEFPF TOFPF TOOK TOKO TECOK TOKEC
Clocks
Setup and Hold Times
ns ns ns ns ns ns ns ns
TCH TCL TMRW TRRI
Global Set/Reset
Notes: 1. Output timing is measured at TTL threshold, with 35 pF external capacitive loads. 2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27.
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CB191/196 Package for XQ4010E
Pin Description Pin Description GND PGCK1_(A16*I/0) I/O_(A17) I/0 I/O I/O_(TDI) I/O_(TCK) I/O I/O I/O I/O GND I/O I/O I/O_(TMS) I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O PG191 D4 C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 C7 A4 A5 B7 A6 C8 A7 B8 A8 B9 C9 D9 D10 C10 B10 A9 A10 A11 C11 B11 A12 CB196 P1 P2 P3 P4 P5(1) P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 Bound Scan 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 191 194 197 200 203 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O SCGK2_(I/O) M1 GND M0 VCC M2 PGCK2_(I/O) I/O_(HDC) I/O I/0 I/O I/O_(LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O PG191 B12 A13 C12 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 D15 A18 D16 C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 G16 E18 F18 G17 G18 CB196 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54(1) P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67
Bound Scan 206 209 212 215 218 221 224 227 230 233 236 239 242 245(2) 246(2) 247 250 253 256 259 262 265 268 271 274 277 280 283 286
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
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Pin Description I/O I/O I/O I/O I/O I/O_(/ERR_/INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK3_(I/O) GND DONE VCC /PROG I/O_(D7)
PG191 H16 H17 H18 J18 J17 J16 J15 K15 K16 K17 K18 L18 L17 L16 M18 M17 N18 P18 M16 N17 R18 T18 P17 N16 T17 R17 P16 U18 T16 R16 U17 R15 V18 T15
CB196 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101
Bound Scan 286 291 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 349 349 352 355 358 361 364 367
Pin Description PGCK3_(I/O) I/O I/O I/O_(D6) I/O I/O I/O I/O I/O GND I/O I/O I/O_(D5) I/O_(/CSO) I/O I/O I/O I/O I/O_(D4) I/O VCC GND I/O_(D3) I/O_(/RS) I/O I/O I/O I/O I/O_(D2) I/O I/O I/O GND
PG191 U16 T14 U15 V17 V16 T13 U14 V15 V14 T12 U13 V13 U12 V12 T11 U11 V11 V1 U10 T10 R10 R9 T9 U9 V9 V8 U8 T8 V7 U7 V6 U6 T7
CB196 P102 P103(1) P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135
Bound Scan 370 376 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 -
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
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Pin Description I/O I/O I/O I/O I/O_(D1) I/O_(RCLK-/BUSY/RDY) I/O I/O I/O_(D0*_DIN) SGCK4_(DOUT*_I/O) CCLK VCC TDO GND I/O_(A0*_WS) PGCK4_(I/O*_A1) I/O I/O I/O_(CS1*_A2) I/O_(A3) I/O I/O I/O I/O GND I/O I/O I/O_(A4) I/O_(A5) I/O I/O I/O
PG191 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 R4 U2 R3 T3 U1 P3 R2 T2 N3 P2 T1 R1 N2 M3 P1 N1 M2 M1 L3 L2 L1
CB196 P136 P137 P138 T139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152(1) P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168
Bound Scan 457 460 463 446 469 472 475 478 481 484 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50
Pin Description I/O I/O_(A6) I/O_(A7) GND VCC I/O_(A8) I/O_(A9) I/O I/O I/O I/O I/O_(A10) I/O_(A11) I/O I/O GND I/O I/O I/O I/O I/O_(A12) I/O_(A13 I/O I/O_(A14) SGCK1(A15*I/O) VCC
PG191 K1 K2 K3 K4 J4 J3 J2 J1 H1 H2 H3 G1 G2 F1 E1 G3 F2 D1 C1 E2 F3 D2 E3 C2 B2 D3
CB196 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P192(1) P193 P194 P195 P196
Bound Scan 53 56 59 62 65 68 71 74 77 80 83 86 89 92 96 98 101 104 107 113 116 119 -
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
Additional XQ4010E Package Pins
CB196
Notes: 1. Indicates unconnected package pins. 2. Contributes only one bit (.I) to the boundary scan register. Boundary Scan Bit 0 = TD0.T Boundary Scan Bit 1 = TD0.0 Boundary Scan Bit 487 = BSCAN.UPD
No Connect Pins P5 P192 P54 P103 P152 -
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DS021 (v2.2) June 25, 2000 Product Specification
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Ordering Information
XQ 4010E -4 PG 191 M
MIL-PRF-38535 (QML) Processing Device Type XQ4005E XQ4010E XQ4013E XQ4025E XQ4028EX Speed Grade -3 -4 Number of Pins Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array HQ = Plastic Quad Flat Pack BG = Plastic Ball Grid Array Temperature Range M = Ceramic (TC = -55C to +125C) N = Plastic (TJ = -55C to +125C)
Revision History
The following table shows the revision history for this document Date 05/19/98 06/25/00 Version 2.1 2.2 Updates. Updated timing specifications to match with commercial data sheet. Updated format. Description
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